Multimode reconfigurable digital ΣΔ modulator architecture for fractional-N PLLs

Authors:
Sieiman Ball Sleiman;Mohammed Ismail
Affiliations:
Analog VLSI Laboratory, Ohio State University, Columbus, OH;Analog VLSI Laboratory, Ohio State University, Columbus, OH
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

Citing 3
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Abstract

This brief presents the analysis, design, and implementation of a multimode reconfigurable digital Sigma-Delta (ΣΔ) modulator for use in fractional-N phase-locked loops. Analysis of secondo, third-, and fourth-order modulators with respect to PLL phase noise contribution in the presence of loop nonlinearities is performed. Optimal architectures in each order are found and a single reconfigurable modulator is designed and implemented on FPGA. The proposed architecture is able to cover seven different modes of operation and spans three orders, thus offering a great degree of noise-shaping flexibility suitable for multistandard wireless applications. A case study for LTE/WiMAX is further presented for demonstration.