Optimal ΣΔ modulator architectures for fractional-N frequency synthesis

Authors:
Sleiman Bou Sleiman;Jad G. Atallah;Saul Rodriguez;Ana Rusu;Mohammed Ismail
Affiliations:
Analog VLSI Laboratory, Ohio State University, Columbus, OH;Radio and Mixed Signal Integrated Systems Group, Royal Institute of Technology (KTH), Stockholm, Sweden;Radio and Mixed Signal Integrated Systems Group, Royal Institute of Technology (KTH), Stockholm, Sweden;Radio and Mixed Signal Integrated Systems Group, Royal Institute of Technology (KTH), Stockholm, Sweden;Analog VLSI Laboratory, Ohio State University, Columbus, OH and Radio and Mixed Signal Integrated Systems Group, Royal Institute of Technology (KTH), Stockholm, Sweden
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

Citing 2
Cited 1

RF microelectronics

RF microelectronics
An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Analog Integrated Circuits and Signal Processing

Multimode reconfigurable digital ΣΔ modulator architecture for fractional-N PLLs

IEEE Transactions on Circuits and Systems II: Express Briefs

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Abstract

This paper presents a comparative study of ΣΔ modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.