Hardware reduction in digital delta-sigma modulators via error masking: part II: SQ-DDSM

Authors:
Zhipeng Ye;Michael Peter Kennedy
Affiliations:
Australian Semiconductor Technology Company Pty Ltd., Adelaide, South Australia and Department of Microelectronic Engineering, Tyndall National Institute, University College Cork, Cork, Ireland;Department of Microelectronic Engineering, Tyndall National Institute, University College Cork, Cork, Ireland
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

Citing 3
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Abstract

In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs.