Hardware reduction in digital delta-sigma modulators via error masking: part I: MASH DDSM

Authors:
Zhipeng Ye;Michael Peter Kennedy
Affiliations:
Australian Semiconductor Technology Company Pty Ltd., Adelaide, South Australia and Department of Microelectronic Engineering, Faculty of Engineering, University College Cork and Tyndall National ...;Department of Microelectronic Engineering, Faculty of Engineering, University College Cork and Tyndall National Institute, Cork, Ireland
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2009

Citing 2
Cited 2

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Hardware reduction in digital delta-sigma modulators via error masking: part II: SQ-DDSM

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Hardware reduction in digital delta-sigma modulators via error masking: part II: SQ-DDSM

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Spur-free MASH delta-sigma modulation

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Abstract

Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for selecting the word lengths of the stages in multistage architectures are presented. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation and experimental results confirm theoretical predictions. Part I addresses MultistAge noise SHaping (MASH) DDSMs; Part II focuses on single-quantizer DDSMs.