An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer
Analog Integrated Circuits and Signal Processing
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
Integrated Frequency Synthesizers for Wireless Systems
Integrated Frequency Synthesizers for Wireless Systems
An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance
Analog Integrated Circuits and Signal Processing
Analysis and minimization of substrate spurs in fractional-N frequency synthesizers
Analog Integrated Circuits and Signal Processing
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We present an analytical frequency-domain phase-noise model for fractional-N phase-locked loops (PLLs). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump (CP) device noise, and sigma-delta modulator (SDM) noise, including its effect on the in-band phase noise. The thermal device noise of the CP and the turn-on time of the CP output current are found to be limiting the in-band phase noise of state-of-the-art synthesizers. Device noise considerations for bipolar transistors and MOSFETs suggest the use of CMOS-only CPs, even in BiCMOS technologies. We present a noise-optimized CMOS CP specifically designed for a dual-loop PLL architecture using two CPs. This PLL architecture keeps the dc output voltage of the noise-relevant CP and the phase-noise spectrum constant, regardless of temperature variations.