RF microelectronics
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Mismatch shaping techniques to linearize charge pump errors in fractional-N PLLs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance
Analog Integrated Circuits and Signal Processing
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
A high speed, low jitter and fast acquisition CMOS phase frequency detector for charge pump PLL
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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The charge pump (CP) circuit is one of the main building block in a phase-locked loop (PLL) based frequency synthesizers. In conventional CMOS charge pump circuits, there are some non-ideal effects such as clock feed through, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump circuit in 0.18@mm CMOS technology, which greatly reduces the mismatch of current between two branches of the cascode current mirror. By using this proposed architecture, the mismatching between the UP/DN current of the CP can be achieved with less than 0.065% from post-layout simulation. As a result the spur and also the overall phase noise of the PLL are reduced. The charge pump output voltage range is 0.40-1.25V. Additionally, the proposed circuit has wide output voltage swing and high output resistance, which ensures its good performance under very low power supply. Further, this CP circuit is incorporated with a new switching circuit to eliminate the clock feed through and charge injection error.