Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs

Authors:
Tsung-Hsien Lin;Ching-Lung Ti;Yao-Hong Liu
Affiliations:
Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;MStar Semiconductor, Inc., Hsinchu, Taiwan and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Year:
2009

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Abstract

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (ΔΣ) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz ΔΣ fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-µm CMOS process. The fully-integrated ΔΣ fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage.