2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
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In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-@mm CMOS technology and was investigated at a power supply of 1.8V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed.