Spur-reduction frequency synthesizer exploiting randomly selected PFD

Authors:
Te-Wen Liao;Jun-Ren Su;Chung-Chih Hung
Affiliations:
Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan;Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan;Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

Citing 1
Cited 1

Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs

IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008

A 400 MHz---1.5 GHz all digital integer-N PLL with a reference spur reduction technique

Analog Integrated Circuits and Signal Processing

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Abstract

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-µm CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.