A high speed, low jitter and fast acquisition CMOS phase frequency detector for charge pump PLL

Authors:
Manas Kumar Hati;Tarun Kanti Bhattacharyya
Affiliations:
Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India
Venue:
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Year:
2012

Citing 1
Cited 1

Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits

A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL

Microelectronics Journal

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Abstract

This paper presents the different design schemes of the phase frequency detector (PFD) and compares with the output simulation results. The circuits that have been considered are the tristate linear D-FF type PFD, conventional Phase frequency Detector (conPFD), precharge type phase frequency detector (ptPFD), ncPFD in zero degree phase offset version, modified ncPFD with π rad phase offset, and TSPC-PFD. Although, PFDs are suffered from non ideal effects, therefore, to eliminate these effects a proposed PFD has been designed. The simulation results are focused on exploring the jitter, power dissipation, phase noise, and output noise of the different PFDs. The different PFD circuits are designed using 0.18μm CMOS process technology with 1.8 V supply voltage.