CMOS wireless transceiver design
CMOS wireless transceiver design
Wireless CMOS frequency synthesizer design
Wireless CMOS frequency synthesizer design
CYCLONE: automated design and layout of RF LC-oscillators
Proceedings of the 37th Annual Design Automation Conference
An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance
Analog Integrated Circuits and Signal Processing
RF oscillator implementation using integrated CMOS surface acoustic wave resonators
Analog Integrated Circuits and Signal Processing
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A 10 GHz fully integrated Voltage Controlled Oscillator ispresented. A 29.7% tuning range is achieved from a 2.5 V powersupply. The phase noise is -113 dBc/Hz at 600 kHz and -127 dBc/Hzat 3 MHz. The VCO is implemented in a 0.25 ìm 4 metal layerstandard CMOS technology. This design will be used to discussdesign and layout issues for high frequency LC-oscillators. Athorough analysis will be made of the contribution of the differentbuilding blocks to the performance of the total circuit.