A 20 GS/s 1.2 V 0.13 µm CMOS switched cascode track-and-hold amplifier

  • Authors:

  • Heather Orser;Anand Gopinath

  • Affiliations:

  • Medtronic Incorporated, MinneapoIis, MN;University of Minnesota, Minneapolis, MN

  • Venue:
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • Year:
  • 2010

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Abstract

A low voltage, low power, high sampling rate track-and-hold amplifier (THA) architecture is proposed. The THA samples at 20 GS/s and combines a distributed amplifier and a switched cascode stage. Power consumption for the circuit is 71 mW and it occupies 0.09 mm2 in 0.13 µm CMOS. The THA delivers up to 34 dB spur-free dynamic range (SFDR) and -32 dB total harmonic distortion (THD) at a supply voltage of 1.2 V. Input return loss remains below -10 dB over all frequencies of interest, while output return loss remains below -15 dB.