A 1/2 × VDD to 3 × VDD bidirectional I/O buffer with a dynamic gate bias generator

  • Authors:

  • Chua-Chin Wang;Chia-Hao Hsu;Yi-Cheng Liu

  • Affiliations:

  • Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan;Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan;Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan

  • Venue:
  • IEEE Transactions on Circuits and Systems Part I: Regular Papers
  • Year:
  • 2010

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper presents a wide-range I/O buffer able to transmit and receive signals of 0.9/1.2/1.8/3.3/5.0 V by using a typical 0.18 µm CMOS process. The Dynamic gate bias circuit in the proposed I/O buffer is composed of two voltage converters, an EOS (Electrical Overstress) protector, and standard logic cells. A High voltage detector detects voltage level of VDDIO and then generates several bias voltages to the Dynamic gate bias circuit. By using the Dynamic gate bias generator to generate appropriate gate drives for the triple-stacked MOS transistors in the Output stage, the gate-oxide overstress and hot-carrier degradation are avoided. A Floating N-well circuit in the proposed I/O buffer is used to remove undesirable leakage current paths. The proposed I/O buffer can operate at 10/40/50/40/10 MHz when VDDIO are biased at 5.0/3.311.8/1.2/0.9 V, respectively. The maximum speed is 50 MHz given a 19 pF load. The mllximum static power consumption is merely 3.9 µW justified by the measurements on silicon.