Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
(1/3) × VDD-to-(3/2) × VDD wide-range I/O buffer using 0.35-µm 3.3-V CMOS technology
IEEE Transactions on Circuits and Systems II: Express Briefs
A 1/2 × VDD to 3 × VDD bidirectional I/O buffer with a dynamic gate bias generator
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Energy-Efficient Double-Edge Triggered Flip-Flop
Journal of Signal Processing Systems
0.9 V to 5 V bidirectional mixed-voltage I/O buffer with an ESD protection output stage
IEEE Transactions on Circuits and Systems II: Express Briefs
A 2íVDD output buffer with PVT detector for slew rate compensation
Microelectronics Journal
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A 5.0/3.3/1.8-V tolerant I/O buffer implemented using typical CMOS 2P4M 0.35-µm process is proposed in this paper. Unlike traditional mixed-voltage-tolerant I/O buffers, the proposed I/O buffer can transmit and receive signals with voltage levels of 5.0/3.3/1.8 V. By using a stacked PMOS and a stacked NMOS at the output stage and a dynamic gate bias generator providing appropriate control voltages for the gates of the stacked PMOS, gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating n-well circuits are used to remove undesirable leakage current paths. The proposed topology can be applied to any technologies with the constraint of VDD