0.9 V to 5 V bidirectional mixed-voltage I/O buffer with an ESD protection output stage

Authors:
Chua-Chin Wang;Ron-Chi Kuo;Jen-Wei Liu
Affiliations:
Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan;Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan;Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

Citing 1
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Abstract

A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit a sub-3 × VDD voltage-level signal without gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-weU circuit. The maximum data rate is measured at 66 MHz for 5/3.3/2.5/1.8/1.2/0.9 V with an equivalent probe capacitive load of 10 pF.