An asynchronous binary-search ADC architecture with a reduced comparator count

Authors:
Ying-Zu Lin;Soon-Jyh Chang;Yen-Ting Liu;Chun-Cheng Liu;Guan-Ying Huang
Affiliations:
Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan;Department of Electrical Engineering, University of California, Los Angeles, CA;Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

Citing 1
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Abstract

This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2N - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balance between power consumption and operation speed. The proof-of-concept 5-bit prototype only consists of a passive track-and-hold circuit, a reference ladder, 9 comparators, 56 switches and 26 static logic gates. This compact ADC occupies an active area of 120 × 50 µm2 and consumes 1.97 mW from a 1-V supply. At 800 MS/s, the effective number of bits is 4.40 bit and the effective resolution bandwidth is 700 MHz. The resultant figure of merit is 116 fJ/conversion-step.