Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
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Input data reuse in compiling window operations onto reconfigurable hardware
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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Hardware/software partitioning is the problem of dividing an application's computations into a part that executes as sequential instructions on a microprocessor (the "software") and a part that runs as parallel circuits on some IC fabric like an ASIC or FPGA (the "hardware"), such as to achieve design goals set for metrics like performance, power, size, and cost. The circuit part commonly acts as a coprocessor for the microprocessor. For example, a video compression application may be partitioned such that most of the frame handling computations execute on a microprocessor, while the compute-intensive DCT (discrete cosine transformation) part of the compression application is offloaded to execute in a fast DCT coprocessor circuit. Circuits can execute some computations thousands of times faster than sequential instructions, due largely to their parallel execution. For example, if a computation consists of 100 multiplications of independent data items, then while a microprocessor would have to execute the multiplications one (or a few) at a time thus requiring hundreds of clock cycles, a circuit could potentially (subject to data availability) execute all 100 multiplications in parallel using 100 multipliers and thus requiring just 1 or a few clock cycles. Energy reductions can also result.