FPGA implementation of a Greedy algorithm for set covering

Authors:
Alberto Aloisio;Vincenzo Izzo;Salvatore Rampone
Affiliations:
Università di Napoli "Federico II", Dipartimento di Scienze Fisiche and INFN, Napoli, Italy;Università di Napoli "Federico II", Dipartimento di Scienze Fisiche and INFN, Napoli, Italy;Università del Sannio, Research Centre on Software Technology and DSGA, Benevento, Italy
Venue:
RTC'05 Proceedings of the 14th IEEE-NPSS conference on Real time
Year:
2005

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Abstract

A version of a new greedy algorithm for approximating minimum set cover is presented. The algorithm, while not randomized, is based on a probability distribution that leads the greedy choice. The algorithm has been specifically tailored to run on platforms with minimal computational hardware. We also describe an implementation based on a FPGA which makes the algorithm suitable for embedded and real-time architectures.