Codesign system performance based on memory configurations

  • Authors:

  • Luiza de Macedo Mourelle;Nadia Nedjah

  • Affiliations:

  • Departamento de Engenharia de Sistemas e Computação, Faculdade de Engenharia, Universidade do Estado do Rio de Janeiro, Rio de Janeiro, RJ, Brasil;Departamento de Engenharia de Sistemas e Computação, Faculdade de Engenharia, Universidade do Estado do Rio de Janeiro, Rio de Janeiro, RJ, Brasil

  • Venue:
  • SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
  • Year:
  • 1999

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Abstract

In the codesign methodology, the system specification is partitioned into hardware and software subsystems. Subsequently, the former is synthesised into custom hardware, while the latter is compiled into processor code. A common target architecture is based on a shared bus using a single-port global memory. Therefore, the system performance is compromised by bus contention. The hardware and software sub systems communicate through either a busy-wait or an interrupt mechanism. This paper presents two alternatives for memory configuration: one uses a dual-port memory to substitute the original single-port shared memory of the target architecture and the other uses a cache memory for the hardware subsystem, while keeping the Single-port shared memory. The dual-port memory configuration aims to avoid bus contention, whereas the cache memory configuration aims to reduce bus contention during the hardware subsystem memory accesses. The objective of this study is to achieve an acceptable performance in terms of the overall execution time of an application.