Mastering MAKE: a guide to building programs on DOS and UNIX systems
Mastering MAKE: a guide to building programs on DOS and UNIX systems
Applying RCS and SCCS
VHDL development system and coding standard
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
VHDL teamwork, organization units and workspace management
Proceedings of the conference on Design, automation and test in Europe
Static analysis tools for soft-core reviews and audits
Proceedings of the conference on Design, automation and test in Europe
Managing Projects with Make
6.3: Improving VHDL Soft-Cores Reuse with Software-like Reviews and Audits Procedures
IVC-VIUF '98 Proceedings of the International Verilog HDL Conference and VHDL International Users Forum
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A Soft-Cores design reuse methodology requires a hierarchical database approach and a new wave of specific tools for exploiting them in heterogeneous and network distributed frameworks. The differences between Soft-Cores, particularly VHDL ones, and software-like build and reuse processes set up the platform for proposing the VHDL-ICE environment as one feasible solution for an adequate adoption of the proposed approach. The availability of frameworks like this for supporting EDA on Internet will ease the establishment of a mature adoption of Soft-Cores design reuse in the intranets and the internet, as part of a Semiconductor Knowledge management policy.