Challenges in the design high-speed clock and data recovery circuits
IEEE Communications Magazine
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High speed serial interfaces represent the new trend for device-to-device communication. These systems require clock recovery modules to avoid clock forwarding. In this paper we present a high-speed clock recovery method usable with low-cost FPGAs. Our proposed solution features increased speed and reduced size compared to existing designs. The method allows a maximum throughput of 400Mbps compared to the vendor supplied solution capable of only 160Mbps. The module was also integrated and tested within a serial transceiver system. Although the implementation is specific to a given vendor, the idea can also be applied to others devices because it uses only generally available components from most vendors.