Challenges in the design high-speed clock and data recovery circuits

Authors:
B. Razavi
Affiliations:
California Univ., Los Angeles, CA
Venue:
IEEE Communications Magazine
Year:
2002

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Abstract

This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random data is addressed. Next, Hogge (1985), Alexander (1975), and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock and data recovery architectures are presented.