2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

Authors:
Yingmei Chen;Zhigong Wang;Li Zhang;Wei Li
Affiliations:
Institute of RF & OE-ICs, Southeast University, Nanjing, China 210096;Institute of RF & OE-ICs, Southeast University, Nanjing, China 210096;Institute of RF & OE-ICs, Southeast University, Nanjing, China 210096;Institute of RF & OE-ICs, Southeast University, Nanjing, China 210096
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2012

Citing 2
Cited 0

A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Challenges in the design high-speed clock and data recovery circuits

IEEE Communications Magazine

Quantified Score

Hi-index	0.00

Visualization

Abstract

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 μm CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3 ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625 MHz clock has a phase noise of 驴83.8 dBc/Hz at 20 kHz offset in response to 2.5 Gb/s PRBS input data (223---1), and the 2.5 Gb/s PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply (excluding output buffers).