Design of high-speed clock and data recovery circuits

Authors:
Tan Kok-Siang;Mohd-Shahiman Sulaiman;Chuah Hean-Teik;Manoj Sachdev
Affiliations:
Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia 63100;Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia 63100;Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia 63100;Department of Electrical & Computer Engineering, University of Waterloo, Waterloo, Canada N2L3G1
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2007

Citing 3
Cited 0

CMOS High-Speed I/Os - Present and Future

ICCD '03 Proceedings of the 21st International Conference on Computer Design
Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits
Challenges in the design high-speed clock and data recovery circuits

IEEE Communications Magazine

Quantified Score

Hi-index	0.00

Visualization

Abstract

This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phase-frequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described.