Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
Design of high-speed clock and data recovery circuits
Analog Integrated Circuits and Signal Processing
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High-speed I/O circuits, once used only for PHYs, are now widelyused for intra-system signaling as well because of their bandwidth,power, area, and cost advantages. This technology enables chipswith over 1 Tb/s of I/O bandwidth today and over 10 Tb/s ofbandwidth by 2010 as both signaling rates and number of high-speedI/Os increase with process scaling. Key technologies that enablethis growth in I/O performance include low-jitter clock circuitsand equalized signaling. An analysis of clock jitter and channelinterference suggests that signaling rates should track transistorperformance to rates of at least 40 Gb/s over boards,back-planes,and short-distance cables.