Adaptive dual-cross search algorithm for block-matching motion estimation
IEEE Transactions on Consumer Electronics
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
Adaptive rood pattern search for fast block-matching motion estimation
IEEE Transactions on Image Processing
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A reconfigurable hardware for one bit transform based multiple reference frame motion estimation
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.01 |
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and high frame rates, the computational complexity of full search (FS) ME algorithm is prohibitively high, while the PSNR obtained by fast search ME algorithms is low. Therefore, in this paper, we propose a new ME algorithm and a high performance reconfigurable systolic ME hardware architecture for efficiently implementing this algorithm. The proposed ME algorithm performs up to three different granularity search iterations in different size search ranges based on the application requirements. Simulation results showed that the proposed ME algorithm performs very close to FS algorithm, even though it searches much fewer search locations than FS algorithm. It outperforms successful fast search ME algorithms by searching more search locations than these algorithms. The proposed reconfigurable ME hardware is implemented in VHDL and mapped to a low cost Xilinx XC3S1500-5 FPGA. It works at 130MHz and is capable of processing high definition and high frame rate video formats in real time. Therefore, it can be used in flat panel displays for frame rate conversion and de-interlacing, and in video encoders.