A high performance reconfigurable motion estimation hardware architecture
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Consumer Electronics
Fast reference frame selection algorithm for H.264/AVC
IEEE Transactions on Consumer Electronics
High performance hardware architectures for one bit transform based motion estimation
IEEE Transactions on Consumer Electronics
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
Low-complexity block-based motion estimation via one-bit transforms
IEEE Transactions on Circuits and Systems for Video Technology
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Two-bit transform for binary block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Constrained One-Bit Transform for Low Complexity Block Motion Estimation
IEEE Transactions on Circuits and Systems for Video Technology
A reconfigurable architecture for multi-frame motion estimation
CSS'11 Proceedings of the 5th WSEAS international conference on Circuits, systems and signals
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Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance reconfigurable hardware architecture of 1BT based multiple reference frame (MRF) ME. The proposed ME hardware architecture performs full search ME for 4 Macroblocks and 4 reference frames in parallel. The proposed hardware is faster than the 1BT based ME hardware reported in the literature even though it is capable of searching in 4 reference frames. MRF ME increases the ME performance at the expense of increased computational complexity. The reconfigurability of the proposed ME hardware is used to statically configure the number and selection of reference frames based on the application requirements in order to trade-off ME performance and computational complexity. The proposed hardware architecture is implemented in Verilog HDL. The MRF ME hardware consumes %65 of the slices in a Xilinx XC2VP30-7 FPGA. It can work at 191 MHz in the same FPGA and is capable of processing 83 1920x1080 full High Definition frames per second.