A reconfigurable architecture for multi-frame motion estimation

Authors:
Huong Ho
Affiliations:
Communications Research Centre Canada, Ottawa, ON, Canada
Venue:
CSS'11 Proceedings of the 5th WSEAS international conference on Circuits, systems and signals
Year:
2011

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Abstract

A reconfigurable hardware architecture for multiframe frame motion estimation (RMF-ME) is presented in this paper. The proposed architecture can be configured to perform block matching (BM) error computations for 4 reference frames (RF) in parallel. For single reference frame configuration, the RMF-ME can perform concurrent BM computations of 4 macro blocks (MB) to support high motion vector (MV) throughput. The BM engine of the RMF-ME performs error computations on the luminance and the chrominance components of the pixel data in order to get accurate motion trajectories. FPGA implementation results show the RMFME circuit supports 1080P video at 123 frames per second (fps). Simulation and hardware implementation results of the RMFME design demonstrate that the proposed architecture is well suited for high resolution, high quality, and high throughput video applications.