High level H.264/AVC video encoder parallelization for multiprocessor implementation

  • Authors:

  • Hajer Krichene Zrida;Abderrazek Jemai;Ahmed C. Ammari;Mohamed Abid

  • Affiliations:

  • Sfax University, Tunisia;Tunisia;Unité de recherche en Matériaux Mesures et Applications (MMA) INSAT;Sfax University, Tunisia

  • Venue:
  • Proceedings of the Conference on Design, Automation and Test in Europe
  • Year:
  • 2009

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Abstract

H.264/AVC (Advanced Video Codec) is a new video coding standard developed by a joint effort of the ITU-TVCEG and ISO/IEC MPEG. This standard provides higher coding efficiency relative to former standards at the expense of higher computational requirements. Implementing the H.264 video encoder for an embedded System-on-Chip (SoC) is a big challenge. For an efficient implementation, we motivate the use of multiprocessor platforms for the execution of a parallel model of the encoder. In this paper, we propose a high-level independent target-architecture parallelization methodology for the development of an optimized parallel model of a H.264/AVC encoder (i.e. a processes network model balanced in communication and computation workload).