A low-power design methodology for high-resolution pipelined analog-to-digital converters
Proceedings of the 2003 international symposium on Low power electronics and design
An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants
Analog Integrated Circuits and Signal Processing
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A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with 62 dB SNDR. The analog power varies linearly from 36 m W at 20 MS/s to 72 m W at 40 MS/s. The ADC was fabricated in 0.18-µm CMOS process and occupies a die area of 1.9 mm2.