Adapting an SoC to ATE Concurrent Test Capabilities
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Hierarchical decomposition algorithm for hardware/software partitioning
Proceedings of the 44th annual Southeast regional conference
An adaptive resource partitioning algorithm for SMT processors
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
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By simulating the operation environment, many device characteristics can be tested in Hardware-In-The-Loop (HIL) simulation systems and time cost determines the value of such project. Conventional task decomposition, scheduling and resource sharing mechanisms could no longer fully exploit the concurrency in complex HIL simulation systems since complex and stateful devices are integrated. A novel concurrent mechanism is proposed in this paper to solve this problem. In this mechanism, by decomposing the testing resources of complex devices in the simulation environment hierarchically, modeling and managing the resource working and occupation status, (1) test operations can work at finer granularities; (2) independent tasks can hold sharing resource access locks and execute on same devices simultaneously; (3) the logic correctness of real devices and simulation system can be maintained. By using this new mechanism, the effect of prevailing task scheduling algorithm can be extended. A Simple simulation experiment demonstrates the new mechanism improves the time cost about 20% under same test conditions.