Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Static scheduling in a reconfigurable hardware environment
Static scheduling in a reconfigurable hardware environment
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
A new concurrent mechanism for distributed hardware-in-the-loop simulation test system
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
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This paper proposes a novel fast technique for partitioning a system into hardware and software components and scheduling the resulting components for execution. The technique maps hierarchical task graphs onto a heterogeneous architecture containing a single sequential processing engine for executing software components and programmable logic for implementing hardware components. The technique uses an iterative improvement algorithm to evaluate placement of components in the hardware and software partitions. It also uses a decomposition phase to alter the number and granularity of tasks evaluated. By doing so, the algorithm can perform early evaluations on fewer, coarse grained tasks and only evaluate smaller granularities as needed to achieve the desired execution time of the task system. The suitability of this technique in finding a solution which meets a given timing constraint on the system is evaluated by comparing it to a iterative improvement algorithm on a typical non-hierarchical task graph where the task granularities are fixed. To show robustness of the approach, the comparison is done for a large number of synthetic task graphs and the results are normalized so that statistical analysis can be performed on the large sample set.