Communicating sequential processes
Communicating sequential processes
A simple approach to specifying concurrent systems
Communications of the ACM
Penelope, an Ada verification system
TRI-Ada '89 Proceedings of the conference on Tri-Ada '89: Ada technology in context: application, development, and deployment
Larch: languages and tools for formal specification
Larch: languages and tools for formal specification
Abstractions for Software Architecture and Tools to Support Them
IEEE Transactions on Software Engineering - Special issue on software architecture
Specification and Analysis of System Architecture Using Rapide
IEEE Transactions on Software Engineering - Special issue on software architecture
Formalizing architectural connection
ICSE '94 Proceedings of the 16th international conference on Software engineering
Communication and Concurrency
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Principles of Programming Languages
Principles of Programming Languages
Hardware Design and Simulation in Val-VHDL
Hardware Design and Simulation in Val-VHDL
An Event-Based Architecture Definition Language
IEEE Transactions on Software Engineering
On the language design and semantic foundation of lcl, a larch/c interface specification language
On the language design and semantic foundation of lcl, a larch/c interface specification language
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Evaluating architectural design decisions early in the design process is critical for cost effective design. Formal analysis can provide such evaluation if architectures are defined in a formal way. This paper describes how VSPEC can be used to formally define an archilectnre during requirements specification. VSPEC is a Larch interface language for VHDL that annotates VHDL entities using the axiomatic style provided by Larch interface languages. Using VHDL's structural definition Support, entities described in this manner are connected to form architectural descriptions. Activation conditions over component inputs define when that component. must perform its transform. In this paper, we formally define a VSPEC component's state and how component states interact in an architecture. A rudimentary formal semantics for component activation is presented and used to define two potential satisfaction criterion.