Parallel processing architecture for the Hitachi S-3800 shared-memory vector multiprocessor

Authors:
Katsuyoshi Kitai;Tadaaki Isobe;Yoshikazu Tanaka;Yoshiko Tamaki;Masakazu Fukagawa;Teruo Tanaka;Yasuhiro Inagami
Affiliations:
-;-;-;-;-;-;-
Venue:
ICS '93 Proceedings of the 7th international conference on Supercomputing
Year:
1993

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Abstract

This paper discusses the architecture of the new Hitachi supercomputer series, which is capable of achieving 8 GFLOPS in each of up to four processors. This architecture provides high-performance processing for fine-grain parallelism, and it allows efficient parallel processing even in an undedicated environment. It also features the newly-developed time-limited spin-loop synchronization, which combines spin-loop synchronization with operating system primitives, and a communication buffer (CB) which caches shared variables for synchronization, thus allowing them to be accessed faster. Three new instructions take advantage of the CB in order to reduce the parallel overhead. The results of performance measurements confirm the effectiveness of the CB and the new instructions.