A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching
Proceedings of the 33rd annual international symposium on Computer Architecture
Regular Expression Matching in Reconfigurable Hardware
Journal of Signal Processing Systems
Deflating the big bang: fast and scalable deep packet inspection with extended finite automata
Proceedings of the ACM SIGCOMM 2008 conference on Data communication
Compact architecture for high-throughput regular expression matching on FPGA
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Extending finite automata to efficiently match Perl-compatible regular expressions
CoNEXT '08 Proceedings of the 2008 ACM CoNEXT Conference
Pattern overlap in bit-parallel implementation of regular expression repetition quantifiers
International Journal of Security and Networks
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In this poster, we present a programmable hardware architecture to speed up the matching of regular expressions. The match engine is modeled as non-deterministic finite automata (NFA) with auxiliary hardware features to process repetition of sub-patterns without unrolling. The computation is table-driven and the system throughput is deterministic. The lookup tables are implemented using ternary content addressable memory (TCAM). The overall table size is approximately equal to the number of transition edges in the NFA. Incremental changes to the pattern set can be accommodated by modifying the contents of the lookup tables without reconfiguring the hardware.