Fast text searching: allowing errors
Communications of the ACM
Flexible pattern matching in strings: practical on-line search algorithms for texts and biological sequences
Fast Regular Expression Matching Using FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
NetFPGA: reusable router architecture for experimental research
Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow
Extending finite automata to efficiently match Perl-compatible regular expressions
CoNEXT '08 Proceedings of the 2008 ACM CoNEXT Conference
Hardware Architecture for High-Performance Regular Expression Matching
IEEE Transactions on Computers
Regular Expression Matching on Graphics Hardware for Intrusion Detection
RAID '09 Proceedings of the 12th International Symposium on Recent Advances in Intrusion Detection
A modular NFA architecture for regular expression matching
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Data structures, algorithms and architectures for efficient regular expression evaluation
Data structures, algorithms and architectures for efficient regular expression evaluation
A NFA-based programmable regular expression match engine
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
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Deep Packet Inspection DPI in Network Intrusion Detection and Prevention Systems NIDPS typically involves the matching of packet payloads against attack signatures in the form of regular expressions regexes. Existing research into the handling of the constrained {min, max} repetition syntax used in many regexes mainly proposes the use of a counting mechanism which avoids inefficient unrolling of the repeated sub-expression. However, many regexes cannot be handled as their format makes them susceptible to the problem of counter overlap. In this paper, we present a memory-centric bit-parallel hardware architecture that overcomes the issue of counter overlap through the use of a bit serial First-In-First-Out FIFO queue. The memory-centric rather than logic-centric nature of the design has the advantage of allowing dynamic updates to individual attack signatures. The solution proposed in this paper is targeted at ASIC and FPGA platforms and we present experimental results for a proof-of-concept design.