ACM Transactions on Programming Languages and Systems (TOPLAS)
Uniformization and hybrid simulation/analytic models of renewal processes
Operations Research
Modeling and analysis of computer system availability
IBM Journal of Research and Development
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp
IEEE Transactions on Computers
Optimistic parallel simulation of continuous time Markov chains using uniformization
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
Computational algorithms for closed queueing networks with exponential servers
Communications of the ACM
Parallel algorithms for simulating continuous time Markov chains
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
A comparative study of parallel algorithms for simulating continuous time Markov chains
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Asynchronous updates in large parallel systems
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Parallelized Direct Execution Simulation of Message-Passing Parallel Programs
IEEE Transactions on Parallel and Distributed Systems
Parallel replicated simulation of Markov chains: implementation and variance reduction
WSC '93 Proceedings of the 25th conference on Winter simulation
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This paper describes a method for simulating a large class of queueing network models with Markovian phase-type distributions on parallel architectures. The method, which is based on uniformization, exploits Markovian properties that permit one to first build schedules of simulation times at which processors ought to synchronize, and then simulate a mathematically correct sample path through the pre-chosen schedule. While the technique eliminates many of the overheads incurred by other synchronization methods, it may suffer when the maximum rate (in simulation time) at which one processor might possibly ever send jobs to another is much larger than the average rate at which it actually does. We show how to reduce these overheads, sometimes doubling the execution rate as a result. We discuss experiments performed on the Intel iPSC/2 and Touchstone Delta architectures, where speedups in excess of 155 are observed on 256 processors.