Trace-driven memory simulation: a survey
ACM Computing Surveys (CSUR)
Address trace compression through loop detection and reduction
SIGMETRICS '99 Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Trace-Driven Memory Simulation: A Survey
Performance Evaluation: Origins and Directions
Program balance and its impact on high performance RISC architectures
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
An efficient single-pass trace compression technique utilizing instruction streams
ACM Transactions on Modeling and Computer Simulation (TOMACS)
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Recent increases in VLSI processor speed and transistor density have not been matched by a proportionate increase in the number of I/O pins used to communicate information on and off chip. Since the number of I/O pins is limited by packaging technology and switching constraints, this trend is likely to continue, and I/O bandwidth will become the primary VLSI system performance bottleneck. This paper analyzes the potential of address and data stream coding in order to reduce bandwidth requirements