Economics of ASIC test development
Economics of design and test for electronic circuits and systems
Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case Study
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Board Test DFT Model for Computer Products
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A condition based maintenance simulation model for controlling the yield of pick and place machines
ICOSSSE'07 Proceedings of the 6th WSEAS international conference on System science and simulation in engineering
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An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate, component functional defect rate and test coverage. A new Yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASKS is given.