Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A Parallel Double-Step CORDIC Algorithm for Digital Down Converter
CNSR '09 Proceedings of the 2009 Seventh Annual Communication Networks and Services Research Conference
Optimized architecture for computing Zadoff-Chu sequences with application to LTE
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
A Hardware-Efficient Algorithm for Real-Time Computation of Zadoff---Chu Sequences
Journal of Signal Processing Systems
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