Optimized architecture for computing Zadoff-Chu sequences with application to LTE

Authors:
Mohammad M. Mansour
Affiliations:
Department of Electrical and Computer Engineering, American University of Beirut, Beirut, Lebanon
Venue:
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Year:
2009

Citing 5
Cited 2

Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD

IEEE Transactions on Computers
An efficient implementation of singular value decomposition rotation transforms with CORDIC processors

Journal of Parallel and Distributed Computing
3G Evolution, Second Edition: HSPA and LTE for Mobile Broadband

3G Evolution, Second Edition: HSPA and LTE for Mobile Broadband
An efficient CORDIC array structure for the implementation ofdiscrete cosine transform

IEEE Transactions on Signal Processing
A Constructive Representation for the Fourier Dual of the Zadoff–Chu Sequences

IEEE Transactions on Information Theory

Sample Clock Offset Detection and Correction in the LTE Downlink

Journal of Signal Processing Systems
A Hardware-Efficient Algorithm for Real-Time Computation of Zadoff---Chu Sequences

Journal of Signal Processing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

An optimized algorithm and a corresponding re-configurable architecture for computing Zadoff-Chu (ZC) complex sequence elements based on the CORDIC algorithm are proposed. The algorithm computes ZC-sequence elements both in time domain and frequency domain using a simple duality relationship. Algorithm transforms are employed to compute the elements recursively and eliminate multipliers with non-constant terms. The algorithm is applied in a searcher block for detecting the physical random access channel (PRACH) in LTE PHY layer. The PRACH transmits a preamble constructed from ZC sequences to establish initial access along with uplink synchronization with the base station. A reconfigurable hardware architecture was implemented to generate these preambles on the fly with high accuracy based on the proposed algorithm, eliminating the need for storing a large number of long complex ZC sequence elements. Simulation results demonstrate that the proposed architecture is capable of achieving detection error rates for LTE PRACH that are close to ideal rates achieved using floating-point precision.