RF microelectronics
Phase-Locked Loop Synthesizer Simulation
Phase-Locked Loop Synthesizer Simulation
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A new architecture for a frequency synthesizer with adjustable output frequency range and channel spacing is introduced. It is intended for the generation of closely spaced frequency channels in the GHz range while producing minimal spurious phase noise components. The architecture employs two independent phase-locked loops that are driven in cascade by a single reference oscillator. This approach provides fine resolution and wide bandwidth as well as low phase noises. The synthesizer can be operated in either of two different modes: nonfractional and mini-denominator fractional modes. The architecture produces no fractional spurs in the first mode and relatively small phase spurs in the second mode. It is simulated that, in an application to a P-GSM 900 system tuning from 890 to 915 MHz with a channel spacing of 200 kHz, the worst case phase spurs are of 驴100 dBc at an offset frequency of 833 kHz and the linear frequency-switching settling time (to 0.01% of frequency increments) is of 128 μs.