Phase-Locked Loop Synthesizer Simulation

• Authors: Giovanni Bianchi
• Venue: Phase-Locked Loop Synthesizer Simulation
• Year: 2005

Phase locked loops (PLLs) are electronic circuits that ensure that a communications signal stays locked on a given frequency. Their design is crucial to the workings of wireless communications systems. Virtually all transceivers use PLLs to synthesize the stable, high frequency oscillations necessary for radio & wireless. This book describes how to calculate PLL performances by using standard mathematical or circuit analysis programs. Theoretical descriptions are limited to the minimum needed to explain how to perform calculations. Although presented methods of analysis can be implemented with many commercial programs, their description always refers to Mathcad and SIMetrix.Table of contentsPreface Chapter 1: Phase-Locked Loop Basics 1.1 Introduction 1.2 PLL Working Principles 1.3 Laplace and Fourier Transforms 1.3.1 Definitions 1.3.2 Basic properties 1.3.3 Transforms of some important functions 1.4 PLL Transfer Functions 1.4.1 PLL stability analysis 1.5 PLL Order and PLL Type 1.6 First-Order PLL 1.7 Second-Order PLL 1.8 References Chapter 2: Loop Components 2.1 Introduction 2.2 Phase Detector 2.2.1 Multiplier as phase detector 2.2.2 Phase frequency detector 2.3 Loop Filter 2.3.1 Reference spur filtering 2.3.2 Loop filters for voltage output phase detectors 2.3.3 Loop filters for charge pump 2.3.4 Loop filter scaling 2.4 VCO 2.4.1 Principle of working 2.4.2 VCO analysis 2.4.3 Phase Noise 2.4.4 Pulling and pushing 2.5 Reference Sources 2.6 Frequency Dividers 2.6.1 Frequency divider phase noise 2.7 References Chapter 3: Fractional-N Frequency Divider 3.1 Introduction 3.2 Single-Accumulator Fractional Divider 3.3 Multiple-Accumulator Fractional Dividers 3.3.1 Z transform 3.3.2 First-order _-_ modulator 3.3.3 Higher-order _-_ converters 3.3.4 Multiple-accumulator fractional-N phase noise 3.4 References Chapter 4: Synthesizer Performance Simulation 4.1 Introduction 4.2 Simulation Techniques 4.3 Phase Noise 4.3.1 Definitions 4.3.2 Phase noise of PLL synthesizer 4.4 Modulation of the PLL 4.4.1 Modulation of the reference oscillator only 4.4.2 Modulation of the VCO only 4.4.3 Dual-point modulation 4.5 Settling Time 4.5.1 Lock-in 4.5.2 Pull-in 4.6 Final Note on Circuit-Based Simulation 4.7 References Chapter 5: Miscellaneous 5.1 Introduction 5.2 PLL Performance Verification 5.2.1 Measurement of PLL frequency response magnitude 5.3 Sampling Phase Detector 5.4 Multiple-Loop PLL 5.4.1 Phase noise of multiple-loop PLL 5.4.2 Transients in multiple-loop PLL 5.4.3 Variations on double-loop architecture 5.5 Direct Digital Synthesizer 5.5.1 Principle of DDS operation 5.5.2 Effects of nonideal components on DDS performance 5.5.3 Enhancements of DDS architecture 5.6 References Index