A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Emulator Environment Based on an FPGA Prototyping Board
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
FPGA Emulation of Quantum Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Phase-Locked Loop Synthesizer Simulation
Phase-Locked Loop Synthesizer Simulation
High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC
International Journal of High Performance Systems Architecture
An FPGA-based linear all-digital phase-locked loop
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
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The work addresses the implementation and performance analysis of a Digital Carrier Synchronizer (DCS), which is a Phase-Locked Loop (PLL), realized using digital circuits. The DCS function is heavily dependent on the Numerically Controlled Oscillator (NCO) and the Loop Filter (LF). The paper examines the performance of two different NCOs and LFs realisation in DCS for modem application. The methods presented are Look Up Table (LUT) and Xilinx ROM based NCO for 1st order and 2nd order based LF. We also developed a mathematical model of DCS and analyzed the performance based on stability, locking-time and tracking range. We propose a synthesizable and portable FPGA emulation environment of a DCS. Moreover, we have developed the DCS architecture with respect to a frequency based mathematical model. Finally, our emulation technique is not only involved with the DCS but also can be customized for any data synchronization system that respects the mathematical model.