Hierarchical multithreading: programming model and system software

  • Authors:
  • Guang R. Gao;Thomas Sterling;Rick Stevens;Mark Hereld;Weirong Zhu

  • Affiliations:
  • Department of Electrical and Computer Engineering, University of Delaware;Center for Advanced Computing Research, California Institute of Technology, and Department of Computer Science, Louisiana State University;Mathematics and Computer Science Division, Argonne National Laboratory;Mathematics and Computer Science Division, Argonne National Laboratory;Department of Electrical and Computer Engineering, University of Delaware

  • Venue:
  • IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
  • Year:
  • 2006

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Abstract

This paper addresses the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and the difficulties of programmer productivity (e.g. explicit locality management and scheduling, performance tuning, fragmented memory, and synchronous global barriers) to dramatically enhance the broad effectiveness of parallel processing for high end computing. We are developing a hierarchical threaded virtual machine (HTVM) that defines a dynamic, multithreaded execution model and programming model, providing an architecture abstraction for HEC system software and tools development. We are working on a prototype language, LITL-X (pronounced "little-X") for Latency Intrinsic-Tolerant Language, which provides the application programmers with a powerful set of semantic constructs to organize parallel computations in a way that hides/manages latency and limits the effects of overhead. This is quite different from locality management, although the intent of both strategies is to minimize the effect of latency on the efficiency of computation. We will work on a dynamic compilation and runtime model to achieve efficient LITL-X program execution. Several adaptive optimizations will be studied. A methodology of incorporating domainspecific knowledge in program optimization will be studied. Finally, we plan to implement our method in an experimental testbed for a HEC architecture and perform a qualitative and quantitative evaluation on selected applications.