Introduction to VLSI Systems
| Hi-index | 14.98 |
A fast burst error-correction decoder is proposed. It can be used for high-speed decoding of a burst error-correcting Fire code having the generator polynomial G(x) = (1 + xC)p(x), where p(x) is irreducible and of degree m and the degree of G (x) is r = c + m, r being the number of redundancy bits. The decoder needs at most r -1 cycles to find both the error burst pattern and its location, whereas conventional decoding needs up to n cycles [1] (n is the number of bits in a codeword), or a fraction of n [2]. The decoding scheme is based on new aspects of the structure of the error syndrome and the parity check matrix of Fire code recently observed by the author. These aspects allow partial syndrome processing in the decoding process. This makes hardware costs relatively low and enables very high-speed decoding. The decoding scheme makes use of modern mapping devices such as programmable read only memories (PROM's) and field programmable logic arrays (FPLA's), resulting in relatively compact and cheap hardware. The encoder/decoder could probably be implemented as a single-chip LSI circuit.