Combined architecture and hardening techniques exploration for reliable embedded system design
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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This paper proposes an enhanced system-level synthesis flow for the design of reliable embedded systems, extending the classical process to introduce fault mitigation properties in the design under consideration. The strategy first explores the adoption of hardening techniques that, given the initial task graph and the user's reliability requirements, introduce redundancies and mapping constraints on the available resources, which possibly expose fault detection/tolerance features. The reliability-aware task graph is then implemented by means of a classical mapping and scheduling approach thus obtaining the hardened implementation. Experimental results are reported to support the validity of the proposal.