CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links
Proceedings of the great lakes symposium on VLSI
Performance evaluation and design trade-offs for wireless network-on-chip architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper illustrates the feasibility of designing a power-efficient millimeter-wave (mm-wave) transceiver for on-chip wireless communication networks. The performance of the on-chip wireless interconnect using mm-wave transceiver was evaluated through both theoretical analysis as well as system-level simulations in Simulink. To reduce the bit error rate degradation due to channel distortion, root-raised-cosine pulse shaping was performed. The simulation results were then used to define the design specifications of individual RF building blocks. Accordingly, a low-power receiver front-end, consisting of a three-stage wideband LNA, and a single-balanced down-conversion mixer, was also designed. The LNA was implemented using a feed-forward structure to extend the bandwidth at no cost in power consumption. The supply voltage of the mixer was reduced to 0.6 V by eliminating the transistor stack. Simulation results showed that the receiver has a 3-dB bandwidth of 19.2 GHz, a peak gain of 26.5 dB, a noise figure lower than 7.8 dB, and an input P1dB of −28 dBm, while consuming only 11.6 mW.