Probabilistic methods for the impact of an SET in combinational logic

Authors:
Sreenivas Gangadhar;Spyros Tragoudas
Affiliations:
Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901;Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901
Venue:
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
Year:
2010

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A Probabilistic Approach to Diagnose SETs in Sequential Circuits

Journal of Electronic Testing: Theory and Applications

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Abstract

A novel method is proposed in order to calculate the probability of an SET resulting into SEU. The method is proposed to calculate the propagation of SET to the output gate at any time instant within the latching window. The method uses symbolic simulation and disjoint covers of appropriately formulated functions to take into consideration re-convergent paths and therefore more accurate calculations. This is evaluated experimentally on the benchmark circuits.