The size and depth of layered Boolean circuits

Authors:
Anna Gál;Jing-Tang Jang
Affiliations:
Dept. of Computer Science, University of Texas at Austin, Austin, TX 78712-1188, USA;Dept. of Computer Science, University of Texas at Austin, Austin, TX 78712-1188, USA
Venue:
Information Processing Letters
Year:
2011

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Abstract

We consider the relationship between size and depth for layered Boolean circuits and synchronous circuits. We show that every layered Boolean circuit of size s can be simulated by a layered Boolean circuit of depth O(slogs). For synchronous circuits of size s, we obtain simulations of depth O(s). The best known result so far was by Paterson and Valiant (1976) [17], and Dymond and Tompa (1985) [6], which holds for general Boolean circuits and states that D(f)=O(C(f)/logC(f)), where C(f) and D(f) are the minimum size and depth, respectively, of Boolean circuits computing f. The proof of our main result uses an adaptive strategy based on the two-person pebble game introduced by Dymond and Tompa (1985) [6]. Improving any of our results by polylog factors would immediately improve the bounds for general circuits.